1. Field of Invention
The present invention relates generally to clock generators for graphics controllers and, more particularly, to programmable interfaces for clock generators.
2. State of the Art
To support different display resolutions, VGA (including SuperVGA and XGA) controllers usually require many different pixel clock frequencies. A programmable clock generator is an ideal and economic device for providing a VGA controller with these varied frequencies. Generally speaking, conventional programmable clock generators include either of two basic types of programming interfaces. These two basic types of programming interfaces are represented in FIG. 1 as a pre-programmed parallel interface and a programmable serial interface.
Clock generator integrated circuits are presently available that include either a parallel interface, a serial interface or both a parallel and a serial interface. The advantage of a parallel interface is its simplicity in selectively accessing one of a plurality of pre-programmed frequencies from a memory. The advantage of a serial interface is that it can be used to load an arbitrary frequency designated by a user into a memory. However, a parallel interface can select only the pre-programmed frequencies stored in memory, while a serial interface requires external programming circuitry, a relatively complex programming procedure, and a dedicated I/O address bus.
FIG. 1 shows a conventional parallel and serial programming interface for a clock generator. The clock generator 2 includes a ROM 4, a RAM 6, (or Registers) a phase locked loop 8 and control logic 10, all of which are interconnected. A frequency output, represented as CLKout 12, provides a programmable frequency output which is compatible with video formats such as VGA, EGA, MCGA, CGA, and MDA. Further, the clock generator supports two frequency programming modes: an internal frequency selection mode and an external frequency program mode. In the internal mode, frequency select lines 14 (labelled FS.sub.0 to FS.sub.n) are used to select a frequency from 2.sup.n pre-programmed frequencies that are stored in the ROM 4.
In the external mode of operation, a user-selected frequency program code is provided through a serial interface. In this mode of operation, any frequency within the available VCO frequency range of the clock generator can be produced at the output CLKout. During serial programming, data related to the desired frequency is provided to the clock generator via signal line 16. The clock generator further includes control lines 18 that provide m serial interface control signals designated CLT.sub.1 to CLT.sub.m in the drawing. The control signals for the serial interface can include, for example, a read/write signal preceded by a pointer reset for at least one clock cycle to request reading or writing into a serial shift-register. Writing occurs by applying a pointer reset followed by a number (e.g., eighteen) of consecutive write cycles to load the shift-register.
Typically, a parallel interface is used for compatibility with standard interface formats, such as the IBM VGA Standard. However, conformance with such a standard restricts the flexibility of these frequency synthesizers because only limited pre-programmed frequencies are available on the integrated circuits.